complete 2026 web-applications
FPGA Logic Simulator
Draw digital circuits, import Verilog, simulate state, inspect waveforms, and estimate FPGA resources in the browser.
The FPGA Logic Simulator runs a digital circuit in a browser tab and shows you what it costs. Draw gates and flip-flops on the canvas, or paste in Verilog and let it build the schematic for you.
What it does
- Simulates gate-level and sequential circuits, with run, pause, single-step, breakpoints, and watchpoints
- Imports Verilog gate primitives, continuous assigns, bus widths, constants, and
always @(posedge clk)blocks for flip-flops, counters, shift registers, and small state machines - Exports flat or hierarchical Verilog, VCD waveforms, and PNG or SVG images
- Bundles a selection into a reusable block, with sub-circuit libraries you can import and export
- Estimates LUT, flip-flop, block RAM, and I/O use against iCE40 and Cyclone IV targets
- Inspects RAM, register, and counter contents while the circuit runs
- Includes a guided tour, tutorials, and challenges for learning digital logic
Fitting the part
The resource estimate is labelled a teaching model rather than a synthesis result, which is honest: it tells you whether a design is roughly the size of the device you picked, not what a vendor toolchain will produce. That is enough for the loop that matters. Change the schematic, watch the state, read the timing diagram, and find out whether the design has outgrown the part before committing to a real build.